• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    PURPOSE: A method and an apparatus for driving data of a plasma display panel(PDP) are provided, which increase a discharge efficiency by causing a stable address discharge with a low data driving voltage. CONSTITUTION: The method for driving data of the plasma display panel(PDP) generating an address discharge by supplying a data voltage from a data voltage supply(Vcc) to a data electrode(20X) for 1 horizontal scan period includes a step of adding a resonant peaking voltage to the data electrode at a rising edge of the data voltage for the above address discharge. The data driving apparatus comprises the data voltage supply, and a base voltage source(GND), and a switching unit for connecting the data voltage supply and the base voltage source to the data electrode selectively by an input control signal, and a resonant circuit part which is installed between the data voltage supply and the switching unit and forms a resonant circuit with a panel and generates a resonant peaking voltage to the data voltage supplied to the data electrode through the switching unit.
    公开号:KR20020090738A
    申请号:KR1020010029737
    申请日:2001-05-29
    公开日:2002-12-05
    发明作者:최정필
    申请人:엘지전자 주식회사；
    IPC主号:
    专利说明:

    Data driving method of plasma display panel and driving device thereof {Data Driving Method of Plasma Display Panel and Driving Apparatus}
    [16] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a data driving method of a plasma display for driving stable addressing discharge with a low data driving voltage and a driving device thereof.
    [17] Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when vacuum ultraviolet rays generated by gas discharge excite the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.
    [18] 1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.
    [19] Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP includes scan electrodes 12Y and sustain electrodes 12Z formed on an upper substrate 10, and data formed on a lower substrate 18. An electrode 20X is provided.
    [20] The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases discharge efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the data electrode 20X is formed, and the phosphor layer 26 is coated on the lower dielectric layer 22 and the partition wall 24. The data electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the data electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper substrate 10 / lower substrate 18 and the partition wall 24.
    [21] The PDP cell of this structure is selected by the counter discharge between the data electrode 20X and the scan electrode 12Y, and then maintains the discharge by the surface discharge between the scan electrode 12Y and the sustain electrode 12Z. In the PDP cell, the fluorescent substance 28 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted outside the cell. As a result, the PDP having cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the cell, that is, the number of sustain discharges, according to the video data.
    [22] The PDP is driven by an ADS (Address and Display Preiod Separated) method in which one frame is divided into several subfields having a different number of discharge times in order to express gray levels of an image.
    [23] Each subfield is further divided into a reset period for uniformly causing discharge, an address period for selecting a discharge cell, and a sustain period for expressing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. Each of the eight subfields is further divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 n (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased. In this way, since the sustain period is different in each subfield, the gray level of the image can be expressed.
    [24] Referring to FIG. 2, the driving waveform of the conventional PDP is largely four periods, and the reset period for uniformizing the initial condition of the panel to a desired state, the address period for selecting the discharge cells, and the gray scale according to the number of discharges are expressed. Is divided into a sustain period and an erase period for erasing the discharge.
    [25] The reset period is divided into a set-up period and a set-down period. In the set-up period, the rising ramp waveform ramp1 is supplied to the scan electrode 12Y, and in the set-down period, the rising ramp waveform ram2 is supplied.
    [26] In the setup period, a weak reset discharge occurs due to the rising ramp waveform ramp1, and wall charges are accumulated in the cell.
    [27] In the set-down period, the wall ramp in the cell is appropriately erased by the falling ramp waveform ramp2 so that the wall charge is reduced to assist the next address discharge without causing an erroneous discharge. In addition, in order to reduce the wall charge, a positive DC voltage Vs is supplied to the sustain electrode 12Z in the set down period. When the scanning electrode 12Y supplied with the falling ramp waveform ramp2 becomes a relative negative polarity (ie) with respect to the sustain electrode 12Z supplied with the positive DC voltage Vs, that is, the polarity is reversed. The wall charges generated during the setup period are reduced.
    [28] In the address period, the address discharge is caused by the scan voltage Vscan applied to the scan electrode 12Y and the data voltage data applied to the data electrode 20X. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.
    [29] In the sustain period, the sustaining discharge is started in the discharge cells in which the triggering pulse TP is supplied to the scan electrode 12Y at the beginning to sufficiently wall charge in the address period. Subsequently, sustain pulses SUSP are alternately supplied to the scan electrode 12Y and the sustain electrode 12Z to maintain sustain discharge during the sustain period so that a desired gray scale is displayed.
    [30] In the erase period, the discharge pulse EP is supplied to the sustain electrode 12Z to stop the discharge.
    [31] 3 is a circuit diagram illustrating a conventional data electrode driver for supplying a data voltage Data to the data electrode 20X.
    [32] 3 and 4, the data electrode driving unit includes a first switch Q H and a second switch Q L disposed between the data voltage source Vcc and the base voltage source GND, and the first switch Q. FIG. H ) and a logic processor 30 for supplying control signals of the second switch Q L. Output terminals of the first switch Q H and the second switch Q L are connected to the data electrode 20X of the panel. The panel is equivalently referred to as "panel capacitor Cp" because it is a capacitor. Here, the first and second switches Q H and Q L are field-effect transistors. The first switch Q H and the second switch Q L are turned on and off by receiving a control signal from a logic processor 30 connected to each gate terminal. The first switch Q H is connected to the data voltage supply source Vcc and the second switch Q L is connected to the ground voltage source GND.
    [33] The logic processor 30 generates a control signal for supplying the data voltage data to the data electrode 20X and supplies it to the gate terminals of the first switch Q H and the second switch Q L. The logic processor 30 supplies a low level control signal to the gate terminal of the first switch Q H and a high level control signal to the gate terminal of the second switch Q L during the address period. The first switch is applied to the (Q H), a control signal of a low state the first switch (Q H) is turned off, the second switch if the control signal of the high state applied to the (Q L) a second switch (Q L ) is turned on. Therefore, the data electrode 20X is connected to the ground voltage source GND through the second switch Q L to maintain the ground potential. In this state, the data electrode 20X maintains the state of the ground potential, and the control signal of the high state is supplied from the logic processing unit 30 to the gate terminal of the first switch Q H , and the second switch Q L. The gate terminal of is supplied with a control signal in a low state. The first switch when the (Q H) is a control signal of the high state the first switch (Q H) is turned on, the second switch if the control signal of low level applied to the (Q L) a second switch (Q L ) is turned off. Accordingly, the data electrode 20X is connected to the data voltage supply source Vcc through the first switch Q H to receive the data voltage data of 60 to 80V, thereby causing address discharge.
    [34] As such, the data voltage data for addressing the data is directly supplied from the data voltage supply source Vcc and driven. In this case, it is necessary to lower the data driving voltage in order to reduce the power consumption of the PDP. However, when the data driving voltage supplied from the data voltage source Vcc is lowered, not only a stable addressing discharge can be predicted but also the efficiency of the addressing discharge becomes low.
    [35] Accordingly, an object of the present invention is to provide a data driving method of a plasma display and a driving apparatus thereof for generating stable addressing discharge at a low data driving voltage to increase discharge efficiency.
    [1] 1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.
    [2] FIG. 2 is a drive waveform diagram for driving a discharge cell of the PDP shown in FIG.
    [3] 3 is a circuit diagram showing a data driver for driving a conventional data electrode.
    [4] FIG. 4 is a waveform diagram for driving the data driver shown in FIG. 3. FIG.
    [5] 5 is a driving waveform diagram for driving a discharge cell of an alternating current 3-electrode surface discharge type PDP according to the present invention;
    [6] 6 is a circuit diagram showing a data driver for supplying a resonance peaking voltage to a data electrode according to the present invention.
    [7] FIG. 7 is a waveform diagram for driving the data driver shown in FIG. 6. FIG.
    [8] FIG. 8 is a waveform diagram illustrating a resonance peaking voltage supplied to the data electrode shown in FIG. 6.
    [9] <Explanation of symbols for main parts of drawing>
    [10] 10: upper substrate 12Y: scanning electrode
    [11] 12Z: Sustain electrode 14: Dielectric layer
    [12] 16: protective film 18: lower substrate
    [13] 20X: Data electrode 24: Bulkhead
    [14] 26: phosphor layer 30, 40: data driver
    [15] Cp: Panel Capacitor Lp: Inductor
    [36] In order to achieve the above object, the data driving method of the plasma display panel according to the present invention includes the step of adding a resonance peaking voltage to the data electrode at the rising point of the data voltage for address discharge.
    [37] The data driving apparatus of the plasma display panel according to the present invention includes a data voltage supply source, a base voltage source, switching means for selectively connecting the data voltage source and the base voltage source to the data electrodes by an input control signal, and a data voltage source and the switching. It is provided between the means to form a resonant circuit with the panel and has a resonant circuit portion for generating a resonance peaking voltage to the data voltage supplied to the data electrode through the switching means.
    [38] Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.
    [39] Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 8.
    [40] Referring to FIG. 5, the driving waveform of the PDP according to the present invention is largely four periods, and a reset period for uniformizing the initial condition of the panel to a desired state, an address period for selecting discharge cells, and a gray scale according to the number of discharges. Is divided into a sustain period for expressing and an erase period for erasing the discharge.
    [41] The reset period is divided into a set-up period and a set-down period. In the set-up period, the rising ramp waveform ramp1 is supplied to the scan electrode 12Y, and in the set-down period, the rising ramp waveform ram2 is supplied.
    [42] In the setup period, a weak reset discharge occurs due to the rising ramp waveform ramp1, and wall charges are accumulated in the cell.
    [43] In the set-down period, the wall ramp in the cell is appropriately erased by the falling ramp waveform ramp2 so that the wall charge is reduced to assist the next address discharge without causing an erroneous discharge. In addition, in order to reduce the wall charge, a positive DC voltage Vs is supplied to the sustain electrode 12Z in the set down period. When the scanning electrode 12Y supplied with the falling ramp waveform ramp2 becomes a relative negative polarity (ie) with respect to the sustain electrode 12Z supplied with the positive DC voltage Vs, that is, the polarity is reversed. The wall charges generated during the setup period are reduced.
    [44] In the address period, the address discharge is caused by the scan voltage Vscan applied to the scan electrode 12Y and the data voltage data applied to the data electrode 20X. In this case, the resonance peaking voltage Vp with respect to the resonance circuit is added to the data voltage data. The address discharge is usually generated immediately after the data voltage data is applied, that is, near the edge, so that the address discharge can be caused by the relatively high data voltage data to which the resonance peaking voltage Vp is added. By adding the resonance peaking voltage Vp, the data voltage data directly supplied from the data voltage supply source Vcc can be lowered. Here, the method of generating the resonance peaking voltage Vp will be described later.
    [45] In this way, after the address discharge is generated using the resonance peaking voltage Vp, the triggering pulse TP is supplied to the scan electrode 12Y at the beginning during the sustain period to maintain the discharge cells in which the wall charges are sufficiently formed in the address period. The discharge is started. Subsequently, sustain pulses SUSP are alternately supplied to the scan electrode 12Y and the sustain electrode 12Z to maintain sustain discharge during the sustain period so that a desired gray scale is displayed.
    [46] In the erase period, the discharge pulse EP is supplied to the sustain electrode 12Z to stop the discharge.
    [47] 6 is a circuit diagram illustrating a data electrode driver for supplying a resonance peaking voltage Vp to the data electrode 20X according to the present invention.
    [48] 6 and 7, the data electrode driver according to the present invention includes a first switch Q H and a second switch Q L disposed between the data voltage source Vcc and the base voltage source GND, and The logic processor 30 for supplying control signals of the first switch Q H and the second switch Q L , and the inductor Lp provided between the data voltage supply source Vcc and the first switch Q H Equipped. The output terminals of the first switch Q H and the second switch Q L are connected to the panel. The panel is equivalently referred to as "panel capacitor Cp" because it is a capacitor. Here, the first and second switches Q H and Q L are field-effect transistors. The first switch Q H and the second switch Q L are turned on and off by receiving a control signal from a logic processor 30 connected to each gate terminal. The first switch Q H is connected to the data voltage source Vcc through the inductor Lp, and the second switch Q L is connected to the base voltage source GND.
    [49] The logic processor 30 generates a control signal for supplying the data voltage data to the data electrode 20X and supplies it to the first switch Q H and the second switch Q L.
    [50] The logic processor 30 supplies a low level control signal to the gate terminal of the first switch Q H and a high level control signal to the gate terminal of the second switch Q L during the address period. The first switch is applied to the (Q H), a control signal of a low state the first switch (Q H) is turned off, the second switch if the control signal of the high state applied to the (Q L) a second switch (Q L ) is turned on. Therefore, the data electrode 20X is connected to the ground voltage source GND through the second switch Q L to maintain the ground potential. In this state, the data electrode 20X maintains the state of the ground potential, and the control signal of the high state is supplied from the logic processing unit 30 to the gate terminal of the first switch Q H , and the second switch Q L. The gate terminal of is supplied with a control signal in a low state. The first switch when the (Q H) is a control signal of the high state the first switch (Q H) is turned on, the second switch if the control signal of low level applied to the (Q L) a second switch (Q L ) is turned off.
    [51] The inductor Lp forms a resonant circuit together with the panel capacitor Cp when the first switch Q H is turned on. The resonant circuit generates a resonance peak voltage Vp, which is a resonance waveform, by forming a resonance point between the reactance of the inductor Lp and the reactance of the panel capacitor Cp at the turn-on time of the first switch Q H. To be supplied to the data electrode 20X.
    [52] As shown in FIG. 8, the resonance peaking voltage Vp is supplied to the data electrode 20X during the rising period of the data voltage data.
    [53] The resonance peaking voltage Vp is determined by the inductance value L of the inductor Lp and the panel capacitor Cp capacitance C as shown in Equation 1 below.
    [54]
    [55] Therefore, the inductance value L of the inductor Lp is set differently according to the size of the panel capacitor Cp, that is, the size of the PDP in consideration of the resonance peaking voltage Vp.
    [56] Since the address discharge at the resonance peaking voltage Vp has a relatively high initial data voltage, the voltage difference with the scan pulse Vscan supplied to the scan electrode 12Y becomes very large so that the address discharge starts. do. Subsequently, even when a relatively low data voltage data is supplied by canceling the resonance peaking voltage Vp, sufficient wall charges are generated at the initial stage of discharge, thereby maintaining wall charges until other cells are selected.
    [57] Accordingly, even when the data voltage data applied directly from the data voltage source Vcc to the data electrode 20X by the resonance peaking voltage Vp is supplied as low as the maximum voltage of the resonance peaking voltage Vp, the address discharge is sufficiently caused. Can cause. As a result, the driving voltage of the data voltage source Vcc can be lowered by the resonance peaking voltage Vp.
    [58] As described above, the data driving method and its driving apparatus of the plasma display according to the present invention can cause stable address discharge by adding the resonance peaking voltage to the rising point of the data voltage. As a result, the address discharge efficiency is improved.
    [59] In addition, since the data driving voltage can be lowered by the resonance peaking voltage, power consumption can be reduced.
    [60] Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
    权利要求:
    Claims (4)
    [1" claim-type="Currently amended] 1. A data driving method of a plasma display panel in which an address discharge is generated by supplying a data voltage from a data voltage source to a data electrode during a horizontal syringe.
    And adding a resonance peaking voltage to the data electrode at the rising point of the data voltage for the address discharge.
    [2" claim-type="Currently amended] A data driving apparatus of a plasma display panel for driving data electrodes for address discharge,
    Data voltage source,
    Base voltage source,
    Switching means for selectively connecting said data voltage supply source and said base voltage source with said data electrode by an input control signal;
    And a resonant circuit portion provided between the data voltage supply source and the switching means to form a resonant circuit with the panel to generate a resonance peaking voltage to the data voltage supplied to the data electrode through the switching means. Data driver of display panel.
    [3" claim-type="Currently amended] The method of claim 2,
    The switching means
    A first switch for supplying the data voltage supplied from the data voltage supply source to the data electrode according to the input control signal;
    And a second switch for supplying the ground electrode supplied from the base voltage source to the data electrode according to the input control signal.
    [4" claim-type="Currently amended] The method of claim 2,
    And the resonant circuit part is an inductor.
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    同族专利:
    公开号 | 公开日
    KR100385883B1|2003-06-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-05-29|Application filed by 엘지전자 주식회사
    2001-05-29|Priority to KR20010029737A
    2002-12-05|Publication of KR20020090738A
    2003-06-02|Application granted
    2003-06-02|Publication of KR100385883B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20010029737A|KR100385883B1|2001-05-29|2001-05-29|Data Driving Method of Plasma Display Panel and Driving Apparatus thereof|
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